1. Field of the Invention:
This invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device in which both transistor elements and MOS elements are mounted on a single semiconductor substrate and to a method of manufacturing such a semiconductor device.
2. Description of the Related Art:
There is currently known a semiconductor device in which both bipolar transistor elements and MOS elements are mounted on a single semiconductor substrate. In such semiconductor device, as disclosed in an article entitled "A Subnanosecond Bi-CMOS Gate-Array Family", IEEE 1986 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp. 63-66, an emitter electrode of the transistor element and a gate electrode of the MOS element are formed in a common layer, which is usually a polycrystalline silicon layer.
A prior art semiconductor device of this type is shown in FIG. 6 of the accompanying drawings. To fabricate this device, an n.sup.+ -type buried layer 12 and a p.sup.+ -type buried layer 14 are formed on a p-type silicon substrate 10. An n-type epitaxial silicon layer 16 is grown on layers 12 and 14 and a p-type well 18, a p.sup.+ -type channel stopper 20 and a field oxide film 21 are formed in n-type epaxial grown silicon layer 16.
Then, on the surface of the resulting semiconductor substrate, a gate oxide film 22 is formed by thermal oxidation, and at a bipolar-transistor forming region 100, a p-type base region 24 is selectively formed by ion implantation, after which an emitter opening 23 is formed in gate oxide film 22 and over the entire surface shown in FIG. 6, including emitter opening 23 and gate oxide film 22, a polycrystalline silicon layer is formed for producing an emitter electrode 26 and a gate electrode 28.
Subsequently, after adding an n-type impurity such as phosphorous or arsenic to the entire surface of the substrate, i.e. to the polycrystalline silicon layer, by ion implantation, the semiconductor stacked substrate is annealed at a predetermined temperature in a predetermined atmosphere to form an n.sup.+ emitter region 30, whereupon the polycrystalline silicon layer, except portions which are to provide an emitter electrode 26 and a gate electrode 28, is removed.
Thus, at the transistor forming region 100, an npn bipolar transistor 110 is formed.
Then at a MOS-element forming region 200, an n.sup.+ type source and drain regions 32 are selectively formed by ion implantation. Thus, in the MOS-element forming region 200, an n-channel MOSFET 210 is formed.
In such a prior semiconductor device, the oxide film of the bipolar transistor 110 and that of the n-channel MOSFET 210 are formed as a common film 22, and also both the emitter electrode 26 and the gate electrode 28 are formed as a common film, thus simplifying the production process. Consequently, in the bipolar transistor 110, the oxide film 22 which serves as an insulator between the emitter electrode 26 and the p-type base region 24 must be formed so as to have a thickness equal to that of the gate oxide film 22 of the MOSFET 210. The resulting bipolar transistor 110 will, as a result, have a bad high frequency characteristic.
Between the emitter electrode 26 and the base region 24 in this bipolar transistor 110 there is a parasitic capacitance C.sub.EB corresponding to the thickness of the oxide film 22. In the meantime, as advances have been made in recent years in making MOSFETs smaller, there is a trend toward thinner gate oxide films. However, the thinner the gate oxide film of the MOSFETs, the more the parasitic capacitance C.sub.EB of the associated bipolar transistors will increase. Therefore, as the dimensions of the MOS elements are reduced, the high frequency characteristic of the bipolar transistors 110 will be lowered.